1. Field of the Invention
The invention relates to the fabrication of semiconductor devices and, more particularly, the invention relates to a method and apparatus for reducing the amount of charges that are trapped between layers of a semiconductor device during its fabrication.
2. Description of the Background Art
Integrated circuits fabricated on semiconductor substrates for Ultra Large Scale Integration (ULSI) require multiple levels of interconnections for electrically connecting the discrete semiconductor devices that comprise the circuits. Conventionally, the multiple levels of interconnections are separated by layers of insulating material. These interposed insulating layers have etched via holes which are used to connect one level of interconnections to another. Typically, the insulating layer material is silicon oxide (SiO2) having a dielectric constant (relative to vacuum) of about 4.1 to 4.5. As device dimensions decrease and the device density increases, it is necessary to reduce the spacing between the interconnection levels to effectively connect the integrated circuits. Unfortunately, as the spacing decreases, the intra-(on the same metal level) and interlevel (between metal levels) capacitances increase when insulating layers therebetween have the same dielectric constant. The capacitance C is inversely proportional to the spacing d between the levels by the relationship C=keA/d where k is the dielectric coefficient, e is the permittivity of the insulator, A is the area, and d is the spacing between lines. Therefore, it is very desirable to minimize the dielectric constant k in the insulating layers between the interconnection layers to reduce the RC time constant and thereby increase the performance of the circuit (frequency response). The signal propagation time in the circuit is adversely affected by the RC delay time, where R is the resistance of the metal line, and C is the inter- and/or the intralevel capacitance mentioned above.
In greater detail, FIG. 1 depicts an integrated circuit device 100 that is presently known in the art. Typically the device 100 is comprised of a substrate material 102 (typically a dielectric material such as SiO2) having a plurality of layers 103 of various materials disposed thereupon. The various layers have different electrical properties so as to create conductive pathways, circuit devices, and the like. For example, a first layer 104 is an insulating layer disposed on top of the substrate 102 acting as a primary insulator. Within the insulating layer 104 are various circuit pathways or circuit devices 106 comprised of conductive material such as titanium or aluminum. Disposed above the insulating and conductive layers, 104 and 106 respectively, is a second insulative layer 108. Typically, the second insulative layer 108 is a dielectric material but not necessarily the same material as the first dielectric layer 104.
One approach to minimize the RC time delays is to use a good electrical conductor for the interconnection levels, such as replacing the titanium or aluminum with copper to reduce resistance R. A second approach is to use an insulating material that has a lower dielectric constant k, such as an organic, to reduce the capacitance C between the interconnection levels. As such, it is highly favorable to use low k dielectric materials for the second insulative layer 108. One example of a typical low k dielectric material that is currently in use for the fabrication of integrated circuits is the compound trimethylsilane (3MS). The dielectric constant of this material is approximately 2.7; therefore, is highly preferred for use as a dielectric material between conductive areas such as conductive pathways and devices and the like represented as 106.
A well known method for creating integrated circuits such as those described above is by chemical vapor deposition (CVD). Typically, a precursor gas is mixed with a carrier gas and introduced to a deposition chamber at an elevated temperature. Upon contact with a substrate 102 within the chamber, the precursor gas decomposes into various elements and reacts with the surface to create the desired material, such as an insulative layer 104, which is typically an oxide, or a conductive material 106 like copper, for example. Such processes may also be enhanced by the use of a plasma within the chamber which provides for a more uniform deposition process, i.e., when filling an opening in an oxide layer 104 with conductor material 106.
The second insulative layer 108 is also formed by CVD or plasma enhanced CVD; however, deficiencies in the process create undesirable results. For example when depositing one oxide material over another, i.e., second insulative layer 108 deposited over first insulative layer 104, different crystal planar structures and dimensions within these two materials create microscopic gaps at an interface 110 of two such layers. FIG. 2 shows an enlarged detail area of FIG. 1 depicting trapped electrical charges 202 at the interface 110 during the CVD process. These trapped charges 202 create a substantial charge buildup condition within the interface 110 which detrimentally effects nearby devices. For example FIG. 3 depicts a graph of capacitance vs. gate voltage of a device (i.e., the gate structure of a MOSFET transistor device) indicating a flat band voltage of approximately xe2x88x9255 V. Since the charge trapping condition is difficult to avoid, a typical and acceptable value for flat band voltage is approximately xe2x88x9215 V. If there are many such trapped charges 202 at the interface 110, devices constructed on the substrate are detrimentally effected resulting in poor or non-operational condition of such devices.
Therefore, there is a need in the art for a method of semiconductor IC construction and resultant apparatus having low k dielectric material to increase insulative properties, yet not creating the charge trap phenomenon at an interface between such low k dielectric material and other insulative materials used to construct such a device.
The disadvantages associated with the prior art are overcome with the present invention of a method for reducing trapped charges in a semiconductor device having a first layer and a second layer, said method comprising the steps of providing said first layer, flowing a deposition, a dilution and a conversion gas upon said first layer thereby forming a transition layer, phasing out said flow of conversion gas and forming said second layer upon said transition layer. The deposition gas, dilution gas and conversion gas are preferably trimethylsilane, helium and N2O respectively. Additionally, the step of phasing out the conversion gas flow alters the characteristics of the transition layer. The method is formed via chemical vapor deposition or plasma enhanced chemical vapor deposition when depositing the transition layer, first and second layers.
Alternately, a method for reducing trapped charges in a semiconductor device having a first layer and a second layer, said method comprising the steps of providing the first layer, flowing a deposition and dilution gas upon said first layer to form a transition layer thereupon, applying a plasma treatment to said transition layer, and forming said second layer upon said transition layer. The deposition gas and dilution gas are preferably trimethylsilane and helium respectively. Additionally, the plasma treatment further comprises a N2O plasma conducted in a range of approximately 50 to 500 watts and preferably 250 watts. The second layer is preferably a trimethylsilane oxide layer.
An apparatus for reducing trapped charges in a semiconductor device is also disclosed. This apparatus has a first insulating layer, a transition layer disposed upon said first layer and a second insulating layer disposed upon said transition layer. The transition layer improves the adhesion between said first insulating layer and said second insulating layer and said transition layer is preferably a silicon carbide based material and most preferably SiC:H. The second insulating layer is trimethylsilane oxide.
With the method and apparatus described in the subject invention, a reduction in the amount of electrical charges (i.e., ions, electrons or the like) trapped between layers of deposited material is realized. As such, the integrity and quality of devices formed from such layers is improved.